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Computational storage has its first set of official specifications following the publication of version 1.0 of The Storage Networking Industry Association’s Computational Storage Architecture and Programming Model. As reported by The Register, the model is aimed at developing this promising new tech by allowing different manufacturers’ designs to operate together.

For the latest VHDL projects, code snippets, free books, and articles visit the new FPGA’er website

‘Computational storage’ is a new buzzword that doesn’t exactly mean that we’re going to turn SSDs into processors, but that processing and storage will be more tightly bound together, with processors embedded in the storage to share the load of storage-heavy tasks. At the moment, this means an FPGA running encryption, compression and erase tasks under the CPU’s supervision, and could mean an Arm CPU running Linux left to its own devices in the near future. 

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Dr. Gordon Moore was the Director of Research and Development at Fairchild when he wrote the paper, “Cramming More Components onto Integrated Circuits” which was published in the April 19, 1965 issue of Electronics.  Following this publication, Dr. Carver Mead of Caltech declared Dr. Moore’s predictions as “Moore’s Law”.

For the latest VHDL projects, code snippets, free books, and articles visit the new FPGA’er website

Very few people understand the essence of Moore’s Law or know about the myriad of tangential projections Dr. Moore made in this relatively short paper; these included home computers, automatic controls for automobiles, personal portable communications equipment, and many other innovations that at the time may have seemed like science fiction to some readers.

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(We just changed our website address).

The new blog has several new articles and features, in addition to actualizations of articles that were hosted in the past on this website.

Examples:

A series of articles and projects for Digilent’s Basys 3 board (using an Artix-7 FPGA from Xilinx)

New technical articles and code snippets, among them:

• AXI-Lite registers bank
• Xilinx AXI Chip2Chip for multi-FPGA designs
• … and many more!

And a selection of legally free books on FPGAs, VHDL, Machine Learning, Verification, etc.

See you there at fpgaer!

This is meant to be the first among a series of articles about image processing on FPGA. As it is usual on FPGA’er website, articles will include sample code and test benches.

Let’s define some common technology. A digital image is a frame. For starters, we will analyze grayscale images (as opposed to color images). The tiniest element of a digital image is the pixel. A frame is rectangular, composed of lines, and each line is composed of pixels.

So for grayscale frames, we need to know three parameters: Number of lines (m), number of pixels per line(n), and resolution, or depth of each pixel. A usual resolution is 8 bits per pixel, meaning that the gray level for each pixel can have one out of 256 levels, where 0 is black, 255 is white, and any level in the middle is gray, from dark gray to light gray.

Other resolutions (12, 14, 16 bits per pixel) are also common.

There are lots of common frame formats, with nxm taking values of 640 x 480, 1800 x 1200, etc. Most values for n and m are multiples of ‘8’, for obvious reasons in our digital binary world.

An uncompressed frame of 1800 x 1200 pixels, with 8 bits per pixel,  will take roughly 2MByte.

Digital video is a continuous stream of frames. When we talk about digital video, a fourth parameter is introduced: Frame rate, usually measured in frames per second (fps). A digital stream of 1800 x 1200 pixels, with 8 bits per pixel, @60 fps, will have a data rate of more than 120MByte/s. Usually, it will take a bit more, since there is some overhead needed to send line and frame synchronization signals, but this overhead is usually very small.

If we use a parallel bus of 8 bits to send this data, we will need to provide a clock of 120MHz, which is quite reasonable on FPGAs today.

But current cameras usually demand much heavier data rates. It is not uncommon to work with frames of several tens of MegaPixels, resolutions of 12 bits and up, and also faster frame rates.

A 25MPixel camera, with a bit resolution of 12 bits and a frame rate of 160 fps, will need a clock rate of 4GHz. For the connection between camera and FPGA, this translates in the need of physical connection other than a parallel bus, usually LVDS bus or transceivers.

And internally, inside the FPGA, pixels to be processed need to be transmitted in parallel, since we don’t want to exceed a few hundred MHz on our internal FPGA clocks.

Luckily, parallelism is one of the strong points of HW based processing (FPGA, ASIC based). Most of the algorithms of image processing we will discuss in further articles will process bits in parallel.

Keras is a high-level neural networks API, written in Python and capable of running on top of TensorFlow, CNTK, or Theano.

I have recently installed Anaconda, TensorFlow, and Keras in my laptop PC as part of my Deep Machine Learning (DML) plan.

I am reading two books in for my learning effort in parallel: MIT’s Deep Learning book (free online), who provides a strong theoretical background, and Deep Learning with Python. The latter is focused on hands-on training on DML, and it contains almost no math (I must confess this is rather appealing for me).

One of the first examples of the book uses Keras built in IMDB dataset. On this dataset, user’s comments on IMDB movie database were encoded using a dictionary. In such a database, more used words receive smaller encoding numbers, and vice-versa.

The first words are expected: “the”, “and”, “this” and “that” (not strictly the very first ones, but you get the picture”. Among the ten first words, there is one that quizzes me: “br”. Could it be the HTML tag for break?

Anyway, I almost asked myself right away, what are top used words for commentaries, once we set apart the trivial articles and personal pronouns?

My first three words to test were “love”, “hate” and “sex”. I loved the results and told my wife, who proposed several other words. For this article, I concentrated on four of them. You probably already guessed them: Love, hate, sex, and money.

The code to get the words is rather naive. Pardon me, I have just started with Python and Keras. Here it goes:

from keras.datasets import imdb
word_index = imdb.get_word_index()
reverse_word_index = dict([(value, key) for (key, value) in word_index.items()])

i = 1
while i < 10000:
    if reverse_word_index.get(i) == "money":
        print('money is in position ' + str(i))
    if reverse_word_index.get(i) == "love":
        print('love is in position ' + str(i))
    if reverse_word_index.get(i) == "sex":
        print('sex is in position ' + str(i))
    if reverse_word_index.get(i) == "hate":
        print('hate is in position ' + str(i))
    i += 1

If you are waiting for the results, here they are:

Love goes first. Then money, followed by sex. And hate is way on the back.

So if I had to judge the future of humanity, I would say it is quite good, at least based on IMDB reviews.

P.S.: The first two non-trivial words championing the list are, not surprisingly, “film” and “movie”. What words would YOU search on the list?

There have been many announcements about what would be the next generation Intel Xeon platform with integrated FPGA, also on this blog.

Now Intel has finally announced that they are shipping their Xeon 6138P Gold with integrated FPGA accelerator to selected customers.

The Intel Xeon 6138P includes ane Arria10 GX 1150 FPGA core, with up to 160Gbps of I/O bandwidth and a cache-coherent interface for tightly coupled acceleration. The Arria FPGA has its own cache and connects with the Xeon processor via Intel’s ultra fast UPI (Ultra Path Interconnect). The data sharing between processor and FPGA do not need DMA access, reducing programming complexity.

According Anandtech, “The Xeon Scalable Gold 6138 is already an existing CPU, and the x86 silicon on the 6138P looks to be identical between the two parts: A 20C/40T CPU, with a 2GHz base clock, 3.7GHz boost, with 6 channels of DDR4 support. The PCIe lane count is different — 48 lanes on the base 6138 compared with 32 lanes on the 6138P — but this almost certainly means that 16 of those PCIe 3.0 lanes have been diverted for bandwidth for the FPGA.”

According to Intel, the integrated processor Xeon delivers a 3.2x throughput improvement at half the latency compared to an FPGA-less Xeon device.

In the announcement, Intel has stated that “Fujitsu, a lead partner, plans to deliver systems based on the Intel® Xeon® processor with integrated FPGA and Intel’s OVS reference design. They are making the Intel® virtual switching reference design even more robust for the networking environment through their reliability, availability, and serviceability (RAS) with performance monitoring and debug assisting functions. This solution is being demonstrated this week at the Fujitsu Forum in Tokyo.”

For more information:

(Intel) Intel Processors and FPGAs—Better Together

(Anandtech) Intel Shows Xeon Scalable Gold 6138P with Integrated FPGA, Shipping to Vendors

(ExtremeTech) Intel Shows Off Xeon Scalable Gold 6138P With an Integrated FPGA

(NextPlatform) A peek inside that Intel Xeon-FPGA hybrid chip

The first in the projects for the Cyclone V GX Starter kit will be a HW LED flasher. Although the design is very easy, it is a complete design including absolutely all the elements needed to achieve a reliable design with timing closure.

For an introduction about the Cyclone V GX Starter kit evaluation board, please refer to this post.

What will the project do:

1. Flash a sequence of LEDs (red and green) by dividing the clock input
2. Make a ‘lamp test’ (all LEDs lit) when reset is pressed
3. LEDs sequence is accelerated if the user presses the second push button on the board.

The design includes the following blocks:

1. PLL: Takes the 50MHz input to the board and generates an internal 100MHz clock signal.
2. Reset synchronizer: Reset signal is sampled by this block using two flip-flops. Reset is released only on rising edge of internal 100MHz clock. This is the recommended reset connection by Altera for avoiding recovery and removal timing failures. Actually the result is to connect a synchronized reset to the async. reset input of all FFs in the design.
3. top block: Includes a counter to divide the input frequency to blink the LEDs at a speed visible to humans. Also takes care of reset treatment (all LEDs lit) and of LEDs blink acceleration.

The design also includes the following files:

1. QSF including pin assignment
2. SDC – Timing constraint file
3. vhdl source files
4. qip files for Altera generated IP sources

Design directories structure:

• quartus: project files, .qsf file, .sdc file
• src
  • top.vhd and reset_sync.vhd source files
  • ip directory
    • pll1 directory
      • files generated by Altera IP Wizard for ‘pll1’ (50MHz -> 100 MHz)

The design was generated using Quartus Prime 17.0

The project, including all sources and .qar file are available at Github

The comics strip says it all…

… or maybe not.

There are so many missing:

Ethernet, Fast Ethernet, Gigabit Ethernet
The diverse Windows versions… and Unix, and Linux
Serial Rapid IO, Infiniband
PDAs, disc-man, MP3-player, tablets, digital cameras
ADSL, optic fiber, and so many others…

The Cyclone V GX Starter kit is an Evaluation Board (EVB) from Terasic based on Altera’s Cyclone V GX FPGA. The Cyclone V Starter Kit development board includes hardware such as Arduino Header, on-board USB Blaster, audio and video capabilities and much more

On further entries of the blog, I will be including several projects based on this EVB.

The Cyclone V Starter kit board features the following major component blocks:

• Cyclone V GX 5CGXFC5C6F27C7N Device
  • 77K Programmable Logic Elements
  • 4884 Kbits embedded memory
  • Two Hard Memory Controllers
  • Six 3.125G Transceivers
• FPGA configuration circuitry
  • Quad Serial Configuration device – EPCQ256 on FPGA
  • On-Board USB Blaster (Normal Type-B USB connector)
• Memory
  • 4Gb LPDDR2 x32 bits data bus
  • 4Mb SRAM x16 bits data bus
• Interfaces and expansion I/O
  • UART to USB
  • Micro SD Card Socket
  • HSMC x 1(voltage levels: 2.5V), including 4-lanes 3.125G transceiver
  • 2×20 GPIO Header (voltage levels: 3.3V)
  • Arduino header, including analog pins
  • SMA x 4 (DNI), one-lane 3.125G transceiver
• General user input / output
  • 18 LEDs
  • 10 Slide Switches
  • 4 Debounced Push Buttons + 1 CPU reset Push Button
  • Four 7-Segment displays
• Audio/Video
  • HDMI TX, compatible with DVI v1.0 and HDCP v1.4
  • 24-bit CODEC, Line-in, line-out, and microphone-in jacks
• ADC
  • 12-Bit Resolution, 500Ksps Sampling Rate. SPI Interface.
  • 8-Channel Analog Input. Input Range : 0V ~ 4.096V.
• Power
  • 12V DC input

For me, and for many other designers, the first time we saw the internal memory blocks in an FPGA came as a little shock.

Some of us were used to RAM devices used in Board Design. These devices use bidirectional data buses. Even the fastest memories, DDRn DRAMs, use bidirectional data buses (‘n’ has changed over the years, from plain DDR to current DDR4).

So, how come internal memories on an FPGA have TWO data buses? Isn’t that a waste of resources? Why don’t FPGAs have internal tri-state buses?

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